By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins
With the previous few decade efforts on lithography and integrated-circuit (IC) applied sciences, very inexpensive microsystems were effectively constructed for plenty of varied functions. the fashion in instant communications is towards making a networkubiquitous period within the future years. Many extraordinary possibilities and demanding situations, equivalent to layout for multi-standardability and low-voltage (LV) compliance, are speedily changing into the mainstream instructions in wireless-IC study and improvement, on condition that the previous can supply the simplest connectivity between diverse networks, whereas the latter can facilitate the know-how migration into the sub-1-V nanoscale regimes for additional fee and gear aid.
Analog-Baseband Architecturees and Circuits presents architectural and circuit strategies for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the booklet studies the actual layer standards of contemporary instant conversation criteria, provides the basic tradeoffs fascinated with transceiver structure choice, and offers case reports of the cutting-edge multistandard transceivers, the place the most important thoughts bolstered are highlighted and mentioned. A statistical precis (with a hundred+ references brought up) of such a lot used transmitter and receiver architectures for contemporary conversation criteria is equipped. the entire references are citied from the major boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.
The moment half specializes in the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection strategy is disclosed. It, throughout the reconfiguration of receiver and transmitter analog basebands, permits not just a rest of the RF frequency synthesizer’s and native oscillator’s layout requisites, but additionally a good multistandard compliance through synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the primary is established in few layout examples. one in every of them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but additionally encompasses a flexible-IF topology, a different 3D-stack floorplan, and a specific layout technique for prime testability and routability.
The 3rd half offers with the circuit layout. as well as the methodical description of many LV circuit strategies, three tailormade LV-robust practical blocks are offered. They contain: 1) a double-quadrature-downconversion filter out (DQDF) – it realizes at the same time clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon quarter required for understanding a wide time consistent on chip whereas maximizing its highpass-pole switchability for speedy dc-offset transient.
The final half offers experimental result of the three tailored development blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS approach. formerly untold on-/off-chip co-setup for either full-chip and development blocks measurements are defined. not just the construction blocks have effectively prolonged the cutting-edge boundary when it comes to sign bandwidth and provide voltage, the analog-baseband IC has been to this point the lowest-voltage-reported resolution for IEEE 802.11a/b/g WLAN receivers.
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Extra resources for Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers
1. 4. 3a. html J. Ryynänen, K. Kivekäs, J. Jussila, L. Sumanen, A. Pärssinen and K. Halonen, “A Single-chip Multimode Receiver for GSM900, DCS1800, PCS1900, and WCDMA,” IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 4, pp. 594–602, Apr. 2003. I. Ahmed and D. Johns, “A 50MS/s (35mW) to 1kS/s (15µW) Power Scaleable 10b Pipelined ADC with Minimal Bias Current Variation,” IEEE International SolidState Circuits Conference (ISSCC), Digest of Technical Papers, pp. 280–281, Feb. 2005. B. Xia, A.
With such a structure, the I/Q matching required from the following PGA and A/D are very relaxed. The bandwidth of the PGAs and the conversion rate of the A/Ds are reduced to their minimum like zero-IF. The associated overhead is a low cutoff highpass pole in the dc-offset cancellation that is necessary in the PGAs due to a high baseband gain. , four highpass poles). Case-IV positions an analog IF-to-BB downconverter prior to the A/Ds such that the conversion rate of the A/Ds can be minimized. Different from 14 Analog-Baseband Architectures and Circuits Case-III, the dc-offset cancellation for the PGA and LPF is relaxed in its highpass pole frequency.
48] P. 11a WLANs,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 354–355, Feb. 2003. 49] A. 11a Wireless LANs,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 356–357, Feb. 2003. 50] T. 95 GHz Multistandard WLANs,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 90–91, Feb. 2004. 51] J. Maligeorgos and J. 8 GHz Image-Reject Receiver with Wide Dynamic Range,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.
Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins